The present invention generally relates to high performance transistor devices, and more specifically to low threshold voltage, asymmetric MOS transistors having pocket regions of increased dopant concentration located below the transistors' sources or drains.
In circuits comprised of conventional MOS devices, the relationship of maximum frequency f.sub.max to supply voltage and threshold voltage is governed by long and short channel effects of the component devices. As expected, for longer channel devices, the long channel effects predominate and for shorter channel devices, the short channel effects predominate. Most devices exhibit some characteristics of both, with devices having channel lengths between one and two micrometers exhibiting both characteristics about equally. The maximum frequency of circuits comprised of truly long channel devices is given by: EQU .function..sub.max .varies.(V.sub.dd -V.sub.t).sup.2 /V.sub.dd
The same parameter for circuits comprised of truly short channel devices is given by: EQU .function..sub.max .varies.(V.sub.dd -V.sub.t)/V.sub.dd =1-V.sub.t /V.sub.dd
From these equations, it is apparent that the performance (frequency) of a circuit comprised of truly long channel devices is dependent upon the absolute value of the supply voltage, "Vdd." Thus, if the supply voltage to the devices in such circuits is lowered, performance is also lowered. However, in circuits comprised of truly short channel devices, performance is governed by the ratio of threshold voltage to supply voltage (Vt/Vdd). This means that in such circuits the supply voltage to the devices can be lowered with no loss in performance, f.sub.max, so long as the ratio Vt/Vdd is kept constant. For many devices, this relation is nearly true, and it becomes exactly true for devices in which the saturation voltage scales with the supply voltage.
Although low Vt short channel devices appear attractive for the above reason, a problem has been observed with very short channel devices having low threshold voltages. Specifically, the distance between the source and drain regions may be so small that the depletion regions in the channel region adjacent the source and drain can overlap to form a conductive path for charge carriers in the channel region between the source and drain. This results in a phenomenon known as punch through in which current flows through the path created by depletion region, even when the transistor is turned "off" (i.e., the gate voltage does not exceed the threshold voltage).
In high threshold voltage devices, it is known that a "buried electrode" or "ground plane" may be employed to suppress growth of depletion regions in the channel region and thereby prevent punch through. Such devices are described in an article by R. H. Yan, et al., "High Performance 0.1 mm Room Temperature Si MOSFETs," 1992 Symposium on VLSI Technology Digest of Technical Papers, pages 86-87, which is incorporated herein by reference for all purposes. Briefly, a buffed electrode is a region of relatively high dopant concentration extending underneath the channel region and having the same conductivity type as the well. A further advance is described in the U.S. patent application Ser. No. 08/292,513 (previously incorporated herein by reference) which discloses the use of buried electrodes in low threshold voltage devices to prevent punch through.
While low threshold voltage devices having buried electrodes should generally provide improved performance and reduced power consumption, alternative approaches to eliminating the problem of punch through have been explored. One such approach involves devices fabricated with symmetrical halo implants. Halo implants provide pockets of increased dopant concentration (of the same conductivity type as the channel region) in areas underlying the source and drain edges adjacent the channel region. Unlike a buried electrode, the pocket regions of a halo device do not extend underneath the entire channel region. While the performance of some symmetric halo devices has been encouraging, it is believed that further improvements in device performance should be attainable.